1. Field of the Invention
The present invention relates to the field of nanoparticles and nanotechnology, fabrication of nanotechnology, fabrication of patterned and ordered nanotechnology and devices, and fabrication of memory devices such as flash memory devices from the ordered nanoparticles. The invention also relates to the field of fabrication of electronic, electrical and photonic devices using nanotechnology.
2. Background of the Art
A flash memory device is a nonvolatile memory device. Depending on a cell array configuration, the flash memory device may be formed as a NAND flash device, which requires no contact pattern to connect each cell transistor, or a NOR flash device, which has contact patterns for each cell transistor. NAND flash memory, which uses serially configured cell transistors, i.e., a cell string, provides no random access capability but, without the contact patterns, is more suitable for forming highly integrated (mass storage) devices. By contrast, NOR flash memory enables random access but, due to a contact pattern formation for each cell transistor, is less desirable for embodying highly integrated memory devices.
A semiconductor memory device may also be classified as either volatile or non-volatile. Volatile semiconductor memory devices, such as dynamic random access memory (DRAM) devices and/or static random access memory (SRAM) devices, have a relatively high response speed. However, the volatile semiconductor memory devices lose data stored therein when power is shut off. Although non-volatile semiconductor memory devices, such as electrically erasable programmable read only memory (EEPROM) devices and/or flash memory devices, have a relatively slow response speed, non-volatile semiconductor memory devices can maintain data stored therein when power is shut off. In EEPROM devices, data is electrically stored (i.e., programmed) or erased through a Fowler-Nordheim (F-N) tunneling mechanism and/or a channel hot electron injection mechanism.
For example, U.S. Pat. No. 6,465,293 discloses a method of manufacturing a flash memory cell. In accordance with the disclosure in U.S. Pat. No. 6,465,293, a method of manufacturing a flash memory cell includes the steps of forming an oxide layer on a semiconductor substrate in which a device isolation layer is formed, patterning the oxide layer to expose the semiconductor substrate at a portion in which a floating gate will be formed to thereby form an oxide layer pattern, sequentially forming a tunnel insulating layer and a first polysilicon layer on the entire structure, planarizing the first polysilicon layer until the oxide layer pattern is exposed to thereby form a floating gate, etching the tunnel insulating layer and the oxide layer pattern in the exposed portion to a given thickness, forming a dielectric layer on the entire structure, sequentially forming a second polysilicon layer, a tungsten silicide layer and a hard mask, patterning the second polysilicon layer, the tungsten silicide layer and the hard mask to form a control gate, and injecting impurity ions into the semiconductor substrate at the both sides of the floating gate to form a junction region.
The floating gate is self-aligned by the oxide layer pattern partially exposing the semiconductor substrate.
As a packing density of the semiconductor device has become more highly integrated, an aspect ratio of an opening defined by the oxide layer pattern (by which a portion of the semiconductor substrate is exposed) has been increased, thereby generating void(s) in the first polysilicon layer filling up the opening. The void(s) generated in the first polysilicon layer is opened during the planarization process of the first polysilicon layer, and thus an opened seam is formed at a surface of the floating gate. The opened seam deteriorates a breakdown voltage characteristic of the dielectric film formed on the floating gate and a coupling ratio of the flash memory device. Further, leakage current characteristic through the dielectric film is deteriorated.
Another isolation technique called shallow trench isolation (STI) has been introduced to the fabrication of nonvolatile memory devices to reduce the cell size. The conventional field oxides are replaced by STI structures so that the device integration can be effectively improved. However, as component dimensions continue to shrink, the surface area of floating gates also shrinks. This leads directly to a decrease in capacitance of the effective capacitor formed between the floating gate layer and the control gate layer. This decrease in effective capacitance results in a reduction of the capacitive coupling ratio, which is a parameter that describes the coupling to floating gate of the voltage applied to control gate. The poorly-coupled voltage to floating gate limits the programming and accessing speed characteristics of the memory device.
The capacitive coupling ratio Cp is defined by: 1Cp=CcfCcf+Cfs 
where Ccf is capacitance between the control gate and the floating gate; and Cfs is capacitance between the floating gate and the semiconductor substrate.
To improve programming and accessing speeds in nonvolatile memories, many attempts have been made to increase the coupling ratio. It can be understood from the above equation that when the capacitance Ccf between the control gate and the floating gate increases, the coupling ratio Cp increases. Therefore, the coupling ratio Cp is generally increased by increasing the capacitor area between the floating gate and control gate, which increases the capacitance Ccf, and therefore the coupling ratio Cp. For example, U.S. Pat. No. 6,171,909 discloses a method for forming a stacked gate of a flash memory cell. The coupling ratio of the stacked gate is increased by forming a conductive spacer. The conductive spacer, which is a portion of the floating gate, increases the capacitor area between the floating gate and control gate.
Nanotechnology is an anticipated manufacturing technology giving thorough, inexpensive control of the structure of matter through the manipulation of individual atoms. The term has been used to refer to any attempt to work at the submicron scale, but this site mainly covers the subset usually called molecular nanotechnology. Broadly speaking, the central thesis of nanotechnology is that almost any chemically stable structure can be built from a dimensional level that includes final structures having at least one dimension remaining in the realm of from about 0.2 to 50 nanometers. Other dimensions, such as lengths of tubes, may exceed these ranges, but diameters and/or thicknesses may remain within that dimensional realm.
Presently, the vast majority of commercial manufacturing technologies manipulate millions and billions of atoms at a time using conventional shaping technologies. Atoms and molecules are shaped into products by pounding, molding, extruding, deposition, coating, chipping, etching and other large scale mechanical deformation and accumulation technologies. For example, chips can be made by forming pure silicon substrates and then etching and depositing patterns of atoms and molecules on its surface. These techniques depend on large scale manipulation of atomic and molecular materials. The present commercial systems and techniques for the manipulation of molecules and atoms into small masses, such as those associated with nanotechnology is still too high an order of complexity today for existing mass production techniques to be applied to nanotechnology. The quality of the control of the deposition of atomic materials requires the sacrifice of manufacturing speeds to assure quality replication of intended designs. In the future, molecular nanotechnology will require more sophisticated yet high speed control over the placement of individual atoms.
Often, nanotechnology is referred to as “bottom-up” manufacturing. Its aim is to start with the smallest possible building materials, atoms and molecules, and use them to create a desired product. Working with individual atoms and individual molecules allows the atom-by-atom or molecule by molecule design of structures.
Single-wall carbon nanotubes have been made in a DC arc discharge apparatus by simultaneously evaporating carbon and a small percentage of Group VIIIb transition metal from the anode of the arc discharge apparatus. These techniques allow production of only a low yield of carbon nanotubes, and the population of carbon nanotubes exhibits significant variations in structure and size.
A major challenge facing nanotechnology today is the fabrication of electronic and photonic devices in a commercially viable manner. One prerequisite for such commercial applications lies in the ability to enable mass fabrication as well as the ability to create ‘ordering and patterning’ of a large number of nanoparticles in a cost effective manner. One methodology for forming patterned nanotubes is a photolithographic process, such as that described in U.S. Pat. No. 6,960,425 (Jung et al.). In the Jung et al. Patent, a method for forming a pattern of carbon nanotubes includes forming a pattern on a surface-treated substrate using a photolithographic process, and laminating carbon nanotubes thereon using a chemical self-assembly process so as to form the carbon nanotubes in a monolayer or multilayer structure. A monolayer or multilayer carbon nanotube pattern may be easily formed on the substrate, e.g., glass, a silicon wafer and a plastic. Accordingly, the method can be applied to form patterned carbon nanotube layers having a high conductivity, and thus will be usefully utilized in the manufacturing processes of energy storages, for example, solar cells and batteries, flat panel displays, transistors, chemical and biological sensors, semiconductor devices and the like. The technology thus forms the distribution of pattern seeds by photolithography, and then grows the seeds by other deposition methods.
Various methods, apparatus and materials for providing materials for growth of nanotubes are disclosed, for example, in US Patents and Applications such as U.S. Pat. No. 7,052,668, which are incorporated herein by reference in their entirety for their disclosures, as are all other applications, patents and articles referenced herein.
Nanoparticles, conductive nanoparticles of carbon, metals and the like, have been known and enabled to the industry for many years. Examples of US Patent disclosures of such particles and processes are provided, by way of non-limiting examples, in U.S. Pat. Nos. 7,078,276; 7,033,416; 6,878,184; 6,833,019; 6,585,796; 6,572,673; 6,372,077; and the like, each of which are incorporated in their entirety herein by reference.
US Published Application No. 20050164480 discloses methods for making electronic devices with a thin anisotropic conducting layer interface layer formed between a substrate and an active device layer that is preferably patterned conductive layer. The interface layer preferably provides Ohmic and/or rectifying contact between the active device layer and the substrate and preferably provides good adhesion of the active device layer to the substrate. The active device layer is preferably fashioned from a nanoparticle ink solution that is patterned using embossing methods or other suitable printing and/or imaging methods. The active device layer is preferably patterned into an array of gate structures suitable for the fabrication of thin film transistors and the like.
One promising field of use for nanotechnology is in the venue of nano-structured memory devices (e.g., U.S. Pat. Nos. 5,714,766 and 5,937.295), non-volatile memory cells (e.g., U.S. Pat. No. 6,927,136), SONOS memory devices with nano-sized memory traps (U.S. Pat. No. 7,250,653), and Quantum random access memories with nanostructure therein (U.S. Pat. Nos. 6,016,269 and 6,097,627), which are incorporated herein by reference. Methods and materials for production of memory systems and platforms and substrates for nanotechnology memory systems are also disclosed in U.S. Pat. Nos. 6,165,842 and 6,913,984, which are incorporated herein by reference.
U.S. Pat. No. 7,173,304 (Weimer et al.) discloses methods and compositions for forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the first layer of insulating material, forming a plurality of spaced-apart dots of material on the aluminum oxide layer, forming a second layer of insulating material on portions of the aluminum oxide layer not covered by the spaced-apart dots of material, forming a conductive layer above the second layer of insulating material and the plurality of spaced-apart dots of material, and removing excess portions of the layer of conductive material and the second layer of insulating material. A device is disclosed that may include a substrate and a floating gate electrode positioned above a tunnel insulation layer, the floating gate electrode including a layer of insulating material and a plurality of spaced-apart dots of material, each of which have a conductive nano-dot positioned on the dot of material, the dots of material and the conductive nano-dots being positioned in the layer of insulating material. Nanoparticles are deposited on an aluminum oxide layer without ordering of the distribution and location of the nanoparticles in the formation of the gates.
Published U.S. Patent Application No. 20060205132 (Bhattacharyya) describes a scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers. A compatible non-volatile memory transistor can be formed from this basic structure by adding a high-K dielectric constant film with an embedded metal nano-dot layer between the tunnel insulator and the gate stack.
All patents, patent applications and articles cited and referenced herein are incorporated by reference in their entireties.
Nanotechnology has not yet been developed on a commercial scale, but molecular models of possible nanomachines are becoming increasingly common. Often, these models analyze the basic tools necessary for a nanotechnological part that could go into tools such as an assembler. It is a fundamental need of the future of nanotechnology to find basic manufacturing processes and schemes that can be used to mass produce and accurately produce surfaces and materials that provide advances in nanotechnology and its systems.